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| TECHNICAL DATA IN74LV174 Hex D-type flip-flop with reset; positive edge-trigger The 74LV174 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT174. The 74LV174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set- up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. * * * * * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS Supply voltage range: 1.2 to 5.5 V Low input current: 1.0 A; 0.1 A at O = 25 N Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74LV174N Plastic IN74LV174D SOIC IZ74LV174 Chip TA = -40 to 125 C for all packages PIN ASSIGNMENT MR Q0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC Q5 D5 D4 Q4 D3 Q3 CP LOGIC DIAGRAM D0 D1 Q1 D2 Q2 GND FUNCTION TABLE CP Inputs MR CP X Dn X H L L X X Outputs Qn L H L no change no change MR L H PIN 16=VCC PIN 08 = GND H H H H= high level L = low level X = don't care INTEGRAL 1 IN74LV174 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: * 4 Plastic DIP SO Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds Value -0.5 to +5.0 20 50 25 50 50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * IO * 3 ICC IGND PD Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V * 2 VO < -0.5 V or VO > VCC + 0.5 V * 3 -0.5 V < VO < VCC + 0.5 V * 4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA tr, t f DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 1.0 A VCC <2.0 A 2.0 A VCC <2.7 A 2.7 A VCC <3.6 A 3.6 A VCC 5.5 A Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns/V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV174 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol Parameter conditions VCC V -40C to 25C min VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 VI = VIH or VIL IO = -100 A 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 0.2 Guaranteed Limit 85C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.34 3.60 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 1.0 80 0.5 0.5 125C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 1.0 160 0.85 0.85 V Unit VIL LOW level input voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -6 mA VI = VIH or VIL IO = -12 mA VOL LOW level output voltage VI = VIH or VIL IO = 100 A V V V VI = VIH or VIL IO = 6 mA VI = VIH or VIL IO = 12 mA II ICC ICC1 Input current Supply current Additional quiescent supply current per input VI = VCC or 0 V VI =VCC or 0 V IO = 0 A VI =VCC - 0.6 V V V A A mA INTEGRAL 3 IN74LV174 current per input AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL = 1 k, t r=t f=2.5 ns) Test Symbol Parameter conditions VCC V Guaranteed Limit -40C to 25C min tPHL, tPLH Propagation delay CP to Qn VI = 0 V or VCC Figure 1, 4 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 5.5 100 28 21 17 14 100 28 21 17 14 40 19 13 11 9 50 5 5 5 5 50 5 5 5 5 max 200 34 24 20 17 160 34 24 20 17 7.0 34 85C min 140 34 25 20 17 140 34 25 20 17 60 22 16 13 11 50 5 5 5 5 50 5 5 5 5 max 230 43 31 25 21 190 43 31 25 21 125C min 180 41 30 24 20 180 41 30 24 20 80 26 19 15 13 50 5 5 5 5 50 5 5 5 5 max 260 53 39 31 26 220 53 39 31 26 ns Unit tPHL Propagation delay MR to Qn VI = 0 V or VCC Figure 2, 4 ns tW Clock pulse width HIGH or VI = 0 V or VCC LOW Figure 1, 4 ns tW Master reset pulse width LOW VI = 0 V or VCC Figure 1, 4 ns tREM Removal time MR to CP VI = 0 V or VCC Figure 3, 4 ns tSU Set-up time Dn to CP VI = 0 A or VCC enoiie 3, 4 ns th Hold time Dn to CP VI = 0 A or VCC enoiie 2, 4 ns CI CPD fmax Input capacitance Power dissipation capacitance (per flip-flop) Maximum clock pulse frequency OA = 25C VI = 0 V or VCC TA = 25C VI = 0 A or VCC enoiie 1 pF pF 1.2 2.0 2.7 3.0 4.5 - 2.0 16 22 27 32 - 1.0 14 19 24 27 - 1.0 12 16 20 24 MHz INTEGRAL 4 IN74LV174 tw tr CP 10% VM (1 ) tf 90% V1 (2) MR t PHL Q VM (1) V1 (2) GND VOH VOL GND tw 1/fmax tPLH t PHL V OH V OL VM ( 1) Q VM (1 ) t rec CP VM (1) V1 (2) GND Figure 1. Switching Waveforms Figure 2. Switching Waveforms TEST POINT VALID DATA VM (1 ) V1 (2 ) GND t su th V1 VM ( 1) DEVICE UNDER TEST OUTPUT RL * (2 ) CL CP GND * Includes all probe and jig capacitance Figure 3. Switching Waveforms Note: (1) Figure 4. Test Circuit VM = 1.5 V at VCC = 2.7 V VM = 0.5 VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V (2) INTEGRAL 5 IN74LV174 CHIP PAD DIAGRAM 10 15 14 13 12 11 09 1.51+ 0.03 08 16 01 02 Y (0,0) X 03 04 05 06 07 Chip marking LV174 1.53 + 0.03 Location of marking (mm): left lower corner x=1.080, y=0.296 Chip thickness: 0.46 0.02 mm. PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Symbol MR Q0 D0 D1 Q1 D2 Q2 GND CP Q3 D3 Q4 D4 D5 Q5 VCC Location (left lower corner), mm X 0.132 0.132 0.430 0.667 0.902 1.080 1.315 1.315 1.315 1.315 1.017 0.780 0.545 0.367 0.132 0.132 Y 0.295 0.127 0.127 0.127 0.127 0.127 0.127 0.741 1.079 1.247 1.247 1.247 1.247 1.247 1.247 0.633 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 Note: Pad location is given as per metallization layer INTEGRAL 6 |
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